1. Field of the Invention
The present invention relates to a video signal processing circuit for a television receiver, for effecting time axis compression of a first video signal and for inserting the resultant compressed signal into a second video signal, for providing a dual-picture display having a compressed-size picture within a full-size picture.
In particular, the invention relates to a video signal processing circuit whereby such a signal compression and insertion function can be applied to two video signals that are in accordance with respectively different television broadcasting standards.
2. Description of the Related Art
In recent years, accompanying advances in digital technology for video signals, various types of digital television receivers have been developed, and various features have been proposed for these. Among these features is a signal processing circuit which effects time axis compression of a first video signal and inserts the resultant compressed video signal into a second video signal. As a result, a display picture is obtained in which a picture represented by the first video signal appears in compressed size within a full-size picture that is represented by the second video signal. Such a feature has until now been mainly utilized to enable a viewer to simultaneously monitor two different television broadcast channels. However the feature has been extended to allow a picture expressed by a video signal in accordance with one television broadcasting standard (e.g. the PAL standard) to be inserted in compressed size within a picture that is expressed by a video signal in accordance with a different standard (e.g. the NTSC standard, the MUSE standard,
A prior art example of such a video signal processing circuit will be described in the following, referring to the block diagram of FIG. 1, and also to FIG. 2 which shows an example of a display picture that is produced by the operation of such a processing circuit, and FIG. 3 which shows waveforms illustrating the operation. In FIG. 1, numeral 21 denotes a first analog-to-digital (hereinafter, A/D) converter for converting a first analog video signal that is applied to an input terminal IN1, to a digital signal. Numeral 22 denotes a second A/D converter, for effecting conversion to a digital signal of a second analog video signal that is inputted to a second input terminal IN2. Numerals 23 to 26 denote first to fourth demodulator circuits respectively, for demodulating the digital signals that have thus been converted. Numeral 27 denotes a compression circuit for effecting time axis compression of a video signal. Numeral 28 denotes a switching circuit for inserting the compressed second input signal into the first input signal. Numeral 29 denotes a digital-to-analog (hereinafter, D/A) converter for converting the processed digital signal back to analog video signal form. In FIG. 2, numeral 30 denotes the picture that is expressed by the first video signal, and 31 denotes the picture that is expressed by the (time axis compressed) second video signal, which as shown is inserted into the picture 30.
The operation of the above signal processing circuit will be described in the following, referring to FIG. 3. The input video signal that is supplied to the first input terminal IN1 is converted to a digital signal S by the A/D converter 21. The converted digital signal S is inputted to each of two demodulator circuits 23 and 24, to be demodulated and outputted. The demodulator circuits 23 and demodulator circuit 24 are designed for operating on video signals of respectively different television broadcasting standards, for example the PAL standard and the SECAM standard, the PAL standard and the MAC standard, the NTSC standard and the MUSE standard, etc. It will be assumed that output signals will not be simultaneously produced from both the demodulator circuit 23 and the demodulator circuit 24. More specifically, it will be assumed that when a video signal that is in accordance with the television standard of the first demodulator circuit 23 is being applied to the input terminal IN1, there will be no output signal produced from the first demodulator circuit 23, and conversely that when a television signal in accordance with the standard of the second demodulator circuit 24 is being applied, there will be no output signal produced from the first demodulator circuit 23. The video signal that is supplied to the second input terminal IN2 is converted from an analog signal to a digital signal T, by the A/D converter 22. It is then supplied to two demodulator circuits 25 and 26, to be demodulated by the appropriate one of these. The relationships between the demodulator circuit 25 and the demodulator circuit 26 are identical to the relationships between the demodulator circuit 23 and the demodulator circuit 24 described above.
The output signal from the demodulator circuit 25 or the demodulator circuit 26 is subjected to time axis compression by the compression circuit 27, whose operation is based on a memory. Circuits for executing such time axis compression are now very well known in the art, so that detailed description will be omitted here, and also in the description given hereinafter of embodiments of the present invention. At the same time, the compression circuit 27 outputs a switching signal X for use in controlling the insertion of the second video signal V into the first video signal U by a switching circuit 28. That insertion operation can be understood from the waveform diagrams of FIG. 3, in which (b) and (c) show examples of waveforms of the first and second video signals respectively during each of successive horizontal scanning intervals, corresponding to successive horizontal scan lines of the displayed picture. The compressed second video signal is illustrated as waveform (d), which is inserted into the output signal from the switching circuit 28, under the control of the switching signal from the compression circuit 27 (waveform (e)). That is, in response to that switching signal, designated as X, the switching circuit 28 inserts the output signal W from the compression circuit 27, as an insertion signal Y, into the output signal U from the demodulator circuit 23 or from the demodulator circuit 24, and outputs the resultant signal. The output signal from the switching circuit 28, consisting of the first video signal with the compressed second video signal inserted therein, is then converted to an analog signal by the D/A converter 29.
FIG. 2 shows an example of the display that is produced when the second video signal represents the character B while the first video signal represents the character A.
Assuming for example that the demodulator circuits 23 and the 25 are each designed as PAL standard demodulator circuits, and that the demodulator circuits 24 and 26 are each designed as MAC standard demodulator circuits, then when a MAC standard video signal (e.g. supplied to input terminal IN1) is to be compressed and inserted into a PAL standard video signal (e.g. supplied to input terminal IN2), the PAL standard first demodulator circuit 23 and the MAC standard fourth demodulator circuit 26 are used. Conversely, when a MAC standard video signal is to have a PAL standard second video signal compressed and inserted therein, then the MAC standard second demodulator circuit 24 and the PAL standard third demodulator circuit 25 are used.
However with such a prior art signal processing circuit, it is necessary to use a plurality of demodulator circuits, even when these are extremely large-scale circuits such as are required with the MAC standard, or with the MUSE standard. Hence, the overall circuit scale will be large, and the manufacturing cost will be high.
It is an objective of the present invention to overcome the above problems by providing a signal processing circuit whereby it becomes unnecessary to provide a plurality of large-scale demodulator circuits, such as are required for the MAC television standard or MUSE standard.